"One core contains 262,144 programmable synapses and the other contains 65,536 learning synapses."
I'm more curious how one would actually program such a chip, and considering the amount of memory required to parse through a learning dataset, how they interface between external and internal memory. I can't believe it would be a matter of compilers, or what would be the use of the new architecture, especially as they claim it as a departure from the Von Neumann paradigm.
"One core contains 262,144 programmable synapses and the other contains 65,536 learning synapses."
I'm more curious how one would actually program such a chip, and considering the amount of memory required to parse through a learning dataset, how they interface between external and internal memory. I can't believe it would be a matter of compilers, or what would be the use of the new architecture, especially as they claim it as a departure from the Von Neumann paradigm.